Developments Toward a 250-nm, Fully Planarized Fabrication Process With Ten Superconducting Layers And Self-Shunted Josephson Junctions

摘要

We are developing a superconductor electronics fabrication process with up tonine planarized superconducting layers, stackable stud vias, self-shuntedNb/AlOx-Al/Nb Josephson junctions, and one layer of MoNx kinetic inductors. Theminimum feature size of resistors and inductors in the process is 250 nm. Wepresent data on the mutual inductance of Nb stripline and microstrip inductorswith linewidth and spacing from 250 nm to 1 {\mu}m made on the same or adjacentNb layers, as well as the data on the linewidth and resistance uniformity.